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features ? single 2.7v - 3.6v supply ? fast read access time ? 200 ns ? automatic page write operation ? internal address and data latches for 64 bytes ? internal control timer ? fast write cycle times ? page write cycle time: 10 ms maximum ? 1- to 64-byte page write operation ? low power dissipation ? 15 ma active current ?20 a cmos standby current ? hardware and software data protection ? data polling for end of write detection ? high reliability cmos technology ? endurance: 10,000 cycles ? data retention: 10 years ? jedec approved byte-wide pinout ? industrial temperature ranges ? green (pb/halide-free) packaging option only 1. description the at28bv256 is a high-performance elec trically erasable and programmable read- only memory. its 256k of memory is organized as 32,768 words by 8 bits. manufac- tured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation of just 54 mw. when the device is deselected, the cmos standby current is less than 200 a. the at28bv256 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. during a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmel?s at28bv256 has additional features to ensure high quality and manufactura- bility. the device utilizes internal erro r correction for extended endurance and improved data retention characteristics. an optional software data protection mecha- nism is available to guard against inadvert ent writes. the device also includes an extra 64 bytes of eeprom for device identification or tracking. 256k (32k x 8) battery-voltage parallel eeproms at28bv256 0273k?peepr?2/09
2 0273k?peepr?2/09 at28bv256 2. pin configurations 2.1 32-lead plcc ? top view note: 1. plcc package pins 1 and 17 are don?t connect. pin name function a0 - a14 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd dc i/o3 i/o4 i/o5 a7 a12 a14 dc vcc we a13 2.2 28-lead soic ? top view 2.3 28-lead tsop ? top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2
3 0273k?peepr?2/09 at28bv256 3. block diagram 4. absolute maximum ratings* temperature under bias ............. .............. ..... -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v
4 0273k?peepr?2/09 at28bv256 5. device operation 5.1 read the at28bv256 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual-line control gives designers flexibility in prev enting bus contention in their system. 5.2 byte write a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latc hed on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has be en started, it will automati- cally time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectiv ely be a polling operation. 5.3 page write the page write operation of the at28bv256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. each successive byte must be written within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded the at28bv256 will cease accepting data and commence the internal pro- gramming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a6 - a14 inputs. for each we high to low transition during the page write operation, a6 - a14 must be the same. the a0 to a5 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecess ary cycling of other byte s within the page does not occur. 5.4 data polling the at28bv256 features data polling to indicate the end of a write cycle. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. 5.5 toggle bit in addition to data polling, the at28bv256 pr ovides another me thod for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop tog- gling and valid data will be read. reading the toggle bi t may begin at any time during the write cycle. 5.6 data protection if precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. atmel ? has incorporated both hardware and software fe atures that will protect the memory against inadvertent writes.
5 0273k?peepr?2/09 at28bv256 5.6.1 hardware protection hardware features protect against inadvertent writes to the at28bv256 in the following ways: (a) v cc power-on delay ? once v cc has reached 1.8v (typical) th e device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; and (c) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not init iate a write cycle. 5.6.2 software data protection a software-controlled data protection feature has been implemented on the at28bv256. soft- ware data protection (sdp) helps prevent inadvertent writes from corrupting the data in the device. sdp can prevent inadver tent writes during power-up and power-down as well as any other potential period s of system instability. the at28bv256 can only be written using the software data protection feature. a series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. the same three write commands must begin each write opera- tion. all software write commands must obey the page mode write timing specifications. the data in the 3-byte command sequence is not written to the device; the address in the command sequence can be utilized just like any other lo cation in the device. any attempt to write to the devi ce without the 3-byte sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effec- tively be polling operations. 5.7 device identification an extra 64 bytes of eeprom memory are available to the user for device identification. by rais- ing a9 to 12v 0.5v and using address locations 7fc0 h to 7fffh the additional bytes may be written to or read from in the same manner as the regular memory array.
6 0273k?peepr?2/09 at28bv256 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 6. dc and ac operating range at28bv256-20 operating temperature (case) -40c - 85c v cc power supply 2.7v - 3.6v 7. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb v cc standby current cmos ce = v cc - 0.3v to v cc + 1v 50 a i cc v cc active current f = 5 mhz; i out = 0 ma 15 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma 0.3 v v oh output high voltage i oh = -100 a 2.0 v
7 0273k?peepr?2/09 at28bv256 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter at28bv256-20 units min max t acc address to output delay 200 ns t ce (1) ce to output delay 200 ns t oe (2) oe to output delay 0 80 ns t df (3)(4) ce or oe to output float 0 55 ns t oh output hold from oe , ce or address, whichever occurred first 0 ns t ce t oe t df t oh t acc
8 0273k?peepr?2/09 at28bv256 11. input test waveform s and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 20 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
9 0273k?peepr?2/09 at28bv256 note: 1. nr = no restriction. 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )200ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t dv time to data valid nr (1) t oeh t as t ah t ch t cs t wph t wp t dv t ds t dh t oes t oes t oeh t ah t ch t wph t dh t as t cs t wp t dv t ds
10 0273k?peepr?2/09 at28bv256 17. programming algorithm (1)(2)(3) notes: 1. data format: i/o7 - i/o0 (hex ); address format: a14 - a0 (hex). 2. data protect state will be re-activ ated at the end of program cycle. 3. 1 to 64 bytes of data are loaded. 18. software protected program cycle waveforms (1)(2)(3) notes: 1. a0 - a14 must conform to the addressing sequence for the first three bytes as shown above. 2. a6 through a14 must specify the same page address during each high to low transition of we (or ce ) after the software code has been entered. 3. oe must be high only when we and ce are both low. 16. page mode characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 200 ns t blc byte load cycle time 150 s t wph write pulse width high 100 ns load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (3) load last byte to last address (3) enter data protect state writes enabled (2) t as t ah t wp t wph t blc t dh t wc t ds
11 0273k?peepr?2/09 at28bv256 notes: 1. these parameters are characterized and not 100% tested. 2. see ?ac read characteristics? on page 7 . 20. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ?ac read characteristics? on page 7 . 22. toggle bit waveforms notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 19. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns t dh t oeh t oe t wr 21. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns t dh t oe t wr t oeh
12 0273k?peepr?2/09 at28bv256 23. normalized i cc graphs
13 0273k?peepr?2/09 at28bv256 24. ordering information 24.1 green package op tion (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 200 15 0.02 at28bv256-20ju 32j industrial (-40 to 85 c) AT28BV256-20SU 28s at28bv256-20tu 28t package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28s 28-lead, 0.300" wide, plastic gull wing small outline (soic) 28t 28-lead, plastic thin small outline package (tsop) 24.2 die products contact atmel sales for die sales options.
14 0273k?peepr?2/09 at28bv256 25. packaging information 25.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
15 0273k?peepr?2/09 at28bv256 25.2 28s ? soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28s , 28-lead, 0.300" body, plastic gull wing small outline (soic) jedec standard ms-013 b 28s 8/4/03 dimensions in millimeters and (inches). controlling dimension: millimeters. top view side views 0.51(0.020) 0.33(0.013) 7.60(0.2992) 7.40(0.2914) 10.65(0.419) 10.00(0.394) 1.27(0.50) bsc 2.65(0.1043) 2.35(0.0926) 18.10(0.7125) 17.70(0.6969) 0.30(0.0118) 0.10(0.0040) 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 0o ~ 8o pin 1
16 0273k?peepr?2/09 at28bv256 25.3 28t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28t , 28-lead (8 x 13.4 mm) plastic thin small outline package, type i (tsop) c 28t 12/06/02 pin 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-183. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11.80 11.90 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic
0273k?peepr?2/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support p_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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